Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis by Vijay M
165,91 €
1 Introduction. - 1.2 Design Maturity Layers. - 1.3 Proposed Approach. - 1.4 Market Trends. - 1.5 Organization of the Monograph. - 2 Background. - 2.1 The Role of ASICs. - 2.2 ASIC and ASSP design approaches.
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