Logic Synthesis Using Synopsys by Pran Kurup (English) Paperback Book
162,14 €
1.1 ASIC Design Flow Using Synthesis. - 1.2 Design Compiler Basics. - 1.3 Classic Scenarios. - 2 VHDL/Verilog Coding for Synthesis. - 2.1 General HDL Coding Issues. - 2.2 VHDL vs. Verilog: The Language Issue.
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