Routing Congestion in VLSI Circuits: Estimation and Optimization by Prashant Sax
154,50 €
By Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.
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