Low-Power High-Speed ADCs for Nanometer CMOS Integration by Zhiheng Cao (English
125,41 €
(By Zhiheng Cao, Shouli Yan. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2.
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