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Logic Synthesis and Verification Algorithms by Gary D. Hachtel (English) Paperba

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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.

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ISBN-13:

9781475770360
Book Title:

Logic Synthesis and Verification Algorithms
ISBN:

9781475770360

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