Formal Semantics and Proof Techniques for Optimizing VHDL Models by Kothanda Uma
121,58 €
By Kothanda Umamageswaran, Philip A. Wilsey, Sheetanshu L. Pandey. Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL.
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