Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes by Hsia
106,17 €
Modern computing engines—CPUs, GPUs, and NPUs—require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA.
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